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adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 adc12010 12-bit, 10 msps, 160 mw a/d converter with internal sample-and-hold check for samples: adc12010 1 features description the adc12010 is a monolithic cmos analog-to- 23 ? internal sample-and-hold digital converter capable of converting analog input ? outputs 2.4v to 5v compatible signals into 12-bit digital words at 10 megasamples ? pin compatible with adc12020, adc12040, per second (msps), minimum. this converter uses a adc12l063 and adc12l066 differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to ? on-chip reference buffer minimize die size and power consumption while ? power down mode providing excellent dynamic performance. operating on a single 5v power supply, this device consumes applications just 160 mw at 10 msps, including the reference current. the power down feature reduces power ? image processing front end consumption to 25 mw. ? instrumentation the differential inputs provide a full scale input swing ? pc-based data acquisition equal to 2v ref with the possibility of a single-ended ? fax machines input. full use of the differential input is ? wireless local loops/cable modems recommended for optimum performance. for ease of use, the buffered, high impedance, single-ended ? waveform digitizers reference input is converted on-chip to a differential ? dsp front ends reference for use by the processing circuitry. output data format is 12-bit offset binary. key specifications this device is available in the 32-lead lqfp package ? resolution 12 bits and will operate over the industrial temperature range ? conversion rate 10 msps (min) of ? 40 c to +85 c. ? dnl 0.3 lsb (typ) ? enob (f in = 10.1 mhz) 11.3 bits (typ) ? supply voltage +5 / 5 v / % ? power consumption, 10 mhz 160 mw (typ) 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 tri-state is a trademark of texas instruments. 3 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2003 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. connection diagram block diagram 2 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 pin descriptions and equivalent circuits pin no. symbol equivalent circuit description analog i/o non-inverting analog signal input. with a 2.0v reference voltage, the ground- 2 v in + referenced input signal level is 2.0 v p-p centered on v cm . inverting analog signal input. with a 2.0v reference voltage the ground- referenced input signal level is 2.0 v p-p centered on v cm . this pin may be 3 v in ? connected to v cm for single-ended operation, but a differential input signal is required for best performance. reference input. this pin should be bypassed to agnd with a 0.1 f 1 v ref monolithic capacitor. v ref is 2.0v nominal and should be between 1.0v to 2.4v. 31 v rp 32 v rm these pins are high impedance reference bypass pins. connect a 0.1 f capacitor from each of these pins to agnd. do not load these pins. 30 v rn digital i/o digital clock input. the range of frequencies for this input is 100 khz to 15 10 clk mhz (typical) with ensured performance at 10 mhz. the input is sampled on the rising edge of this input. oe is the output enable pin that, when low, enables the tri-state ? data 11 oe output pins. when this pin is high, the outputs are in a high impedance state. pd is the power down input pin. when high, this input puts the converter into the power down mode. when this pin is low, the converter is in the active 8 pd mode. copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: adc12010 v a agnd
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com pin no. symbol equivalent circuit description digital data output pins that make up the 12-bit conversion results. d0 is the 14 ? 19, d0 ? d11 lsb, while d11 is the msb of the offset binary output word. output levels are 22 ? 27 ttl/cmos compatible. analog power positive analog supply pins. these pins should be connected to a quiet +5v 5, 6, 29 v a voltage source and be bypassed to agnd with 0.1 f monolithic capacitors located within 1 cm of these power pins, and with a 10 f capacitor. 4, 7, 28 agnd the ground return for the analog supply. digital power positive digital supply pin. this pin should be connected to the same quiet +5v source as is v a and bypassed to dgnd with a 0.1 f monolithic 13 v d capacitor in parallel with a 10 f capacitor, both located within 1 cm of the power pin. 9, 12 dgnd the ground return for the digital supply. positive digital supply pin for the adc12010's output drivers. this pin should be connected to a voltage source of +2.35v to +5v and be bypassed to dr gnd with a 0.1 f monolithic capacitor. if the supply for this pin is different 21 v dr from the supply used for v a and v d , it should also be bypassed with a 10 f tantalum capacitor. v dr should never exceed the voltage on v d . all bypass capacitors should be located within 1 cm of the supply pin. the ground return for the digital supply for the adc12010's output drivers. this pin should be connected to the system digital ground, but not be 20 dr gnd connected in close proximity to the adc12010's dgnd or agnd pins. see section 5 (layout and grounding) for more details. 4 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 absolute maximum ratings (1) (2) v a , v d 6.5v v dr v d +0.3v |v a ? v d | 100 mv voltage on any input or output pin ? 0.3v to (v a or v d +0.3v) input current at any pin (3) 25 ma package input current (3) 50 ma package dissipation at t a = 25 c see (4) esd susceptibility human body model (5) 2500v machine model (5) 250v soldering temperature, infrared, 10 sec. (6) 235 c storage temperature ? 65 c to +150 c (1) all voltages are measured with respect to gnd = agnd = dgnd = 0v, unless otherwise specified. (2) absolute maximum ratings indicate limits beyond which damage to the device may occur. operating ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. for ensured specifications and test conditions, see the electrical characteristics. the ensured specifications apply only for the test conditions listed. some performance characteristics may degrade when the device is not operated under the listed test conditions. (3) when the input voltage at any pin exceeds the power supplies (that is, v in < agnd, or v in > v a ), the current at that pin should be limited to 25 ma. the 50 ma maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 ma to two. (4) the absolute maximum junction temperature (t j max) for this device is 150 c. the maximum allowable power dissipation is dictated by t j max, the junction-to-ambient thermal resistance ( ja ), and the ambient temperature, (t a ), and can be calculated using the formula p d max = (t j max - t a )/ ja . the values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). obviously, such conditions should always be avoided. (5) human body model is 100 pf capacitor discharged through a 1.5 k resistor. machine model is 220 pf discharged through 0 ? . (6) the 235 c reflow temperature refers to infrared reflow. for vapor phase reflow (vpr), the following conditions apply: maintain the temperature at the top of the package body above 183 c for a minimum 60 seconds. the temperature measured on the package body must not exceed 220 c. only one excursion above 183 c is allowed per reflow cycle. operating ratings (1) (2) operating temperature ? 40 c t a +85 c supply voltage (v a , v d ) +4.75v to +5.25v output driver supply (v dr ) +2.35v to v d v ref input 1.0v to 2.4v clk, pd, oe ? 0.05v to (v d + 0.05v) v in input ? 0v to (v a ? 0.5v) v cm 1.0v to 4.0v |agnd ? dgnd| 100mv (1) absolute maximum ratings indicate limits beyond which damage to the device may occur. operating ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. for ensured specifications and test conditions, see the electrical characteristics. the ensured specifications apply only for the test conditions listed. some performance characteristics may degrade when the device is not operated under the listed test conditions. (2) all voltages are measured with respect to gnd = agnd = dgnd = 0v, unless otherwise specified. package thermal resistance package ja 32-lead lqfp 79 c / w copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: adc12010
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com converter electrical characteristics unless otherwise specified, the following specifications apply for agnd = dgnd = dr gnd = 0v, v a = v d = +5v, v dr = +3.0v, pd = 0v, v ref = +2.0v, f clk = 10 mhz, t r = t f = 3 ns, c l = 25 pf/pin. boldface limits apply for t a = t j = t min to t max : all other limits t a = t j = 25 c (1) (2) (3) units symbol parameter conditions typical (4) limits (4) (limits) static converter characteristics resolution with no missing codes 12 bits (min) inl integral non linearity (5) 0.5 1.5 lsb (max) dnl differential non linearity 0.3 0.9 lsb (max) ge gain error 0.2 2.9 %fs (max) offset error (v in = v in ? ) ? 0.1 1.75 %fs (max) under range output code 0 0 over range output code 4095 4095 dynamic converter characteristics fpbw full power bandwidth 0 dbfs input, output at ? 3 db 100 mhz f in = 1 mhz, v in = ? 0.5 dbfs 70 db snr signal-to-noise ratio f in = 4.4 mhz, v in = ? 0.5 dbfs 70 db f in = 10.1 mhz, v in = ? 0.5 dbfs 70 66 db (min) f in = 1 mhz, v in = ? 0.5 dbfs 70 db sinad signal-to-noise and distortion f in = 4.4 mhz, v in = ? 0.5 dbfs 70 db f in = 10.1 mhz, v in = ? 0.5 dbfs 69 66 db (min) f in = 1 mhz, v in = ? 0.5 dbfs 11.4 db enob effective number of bits f in = 4.4 mhz, v in = ? 0.5 dbfs 11.4 db f in = 10.1 mhz, v in = ? 0.5 dbfs 11.3 10.7 db (min) f in = 1 mhz, v in = ? 0.5 dbfs ? 88 db thd total harmonic distortion f in = 4.4 mhz, v in = ? 0.5 dbfs ? 86 db f in = 10.1 mhz, v in = ? 0.5 dbfs ? 79 ? 74 db (min) f in = 1 mhz, v in = ? 0.5 dbfs 92 db sfdr spurious free dynamic range f in = 4.4 mhz, v in = ? 0.5 dbfs 89 db f in = 10.1 mhz, v in = ? 0.5 dbfs 83 69 db (min) f in = 4.7 mhz and 4.9 mhz, each = ? 7 imd intermodulation distortion ? 75 dbfs dbfs reference and analog input characteristics v cm common mode input voltage v a / 2 v (clk low) 8 pf c in v in input capacitance (each pin to gnd) v in = 2.5 vdc + 0.7 v rms (clk high) 7 pf 1.0 v (min) v ref reference voltage (6) 2.00 2.4 v (max) reference input resistance 100 m (min) (1) the inputs are protected as shown below. input voltage magnitudes above v a or below gnd will not damage this device, provided current is limited per absolute maximum ratings (3) . however, errors in the a/d conversion can occur if the input goes above v a or below gnd by more than 100 mv. as an example, if v a is 4.75v, the full-scale input voltage must be 4.85v to ensure accurate conversions. (2) to ensure accuracy, it is required that |v a ? v d | 100 mv and separate bypass capacitors are used at each power supply pin. (3) with the test condition for v ref = +2.0v (4v p-p differential input), the 12-bit lsb is 977 v. (4) typical figures are at t a = t j = 25 c, and represent most likely parametric norms. test limits are specified to ti ' s aoql (average outgoing quality level). (5) integral non linearity is defined as the deviation of the analog value, expressed in lsbs, from the straight line that passes through positive and negative full-scale. (6) optimum performance will be obtained by keeping the reference input in the 1.8v to 2.2v range. the lm4051cim3-adj (sot-23 package) is recommended for this application. 6 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 dc and logic electrical characteristics unless otherwise specified, the following specifications apply for agnd = dgnd = dr gnd = 0v, v a = v d = +5v, v dr = +3.0v, pd = 0v, v ref = +2.0v, f clk = 10 mhz, t r = t f = 3 ns, c l = 25 pf/pin. boldface limits apply for t a = t j = t min to t max : all other limits t a = t j = 25 c (1) (2) (3) units symbol parameter conditions typical (4) limits (4) (limits) clk, pd, oe digital input characteristics v in(1) logical ? 1 ? input voltage v d = 5.25v 2.0 v (min) v in(0) logical ? 0 ? input voltage v d = 4.75v 1.0 v (max) i in(1) logical ? 1 ? input current v in = 5.0v 10 a i in(0) logical ? 0 ? input current v in = 0v ? 10 a c in digital input capacitance 5 pf d0 ? d11 digital output characteristics v dr = 2.5v 2.3 v (min) v out(1) logical ? 1 ? output voltage i out = ? 0.5 ma v dr = 3v 2.7 v (min) v out(0) logical ? 0 ? output voltage i out = 1.6 ma, v dr = 3v 0.4 v (max) v out = 2.5v or 5v 100 na i oz tri-state output current v out = 0v ? 100 na +i sc output short circuit source current v out = 0v ? 20 ma (min) ? i sc output short circuit sink current v out = v dr 20 ma (min) power supply characteristics pd pin = dgnd, v ref = 2.0v 30 39 ma (max) i a analog supply current pd pin = v dr 2.8 ma pd pin = dgnd 2 2.5 ma (max) i d digital supply current pd pin = v dr , f clk = 0 2.2 ma pd pin = dgnd, c l = 0 pf (5) 0 ma i dr digital output supply current pd pin = v dr , f clk = 0 0 ma pd pin = dgnd, c l = 0 pf (6) 160 207 mw total power consumption pd pin = v dr , f clk = 0 25 mw rejection of positive full-scale error with psrr1+ power supply rejection ratio 69 dbfs v a = 4.75v vs. 5.25v rejection of negative full-scale error with psrr1 ? power supply rejection ratio 51 dbfs v a = 4.75v vs. 5.25v rejection of power supply noise with 10 psrr2 power supply rejection ratio 48 dbfs mhz, 250 mv p-p riding on v a (1) the inputs are protected as shown below. input voltage magnitudes above v or below gnd will not damage this device, provided current is limited per absolute maximum ratings (3) . however, errors in the a/d conversion can occur if the input goes above v a or below gnd by more than 100 mv. as an example, if v a is 4.75v, the full-scale input voltage must be 4.85v to ensure accurate conversions. (2) to ensure accuracy, it is required that |v a ? v d | 100 mv and separate bypass capacitors are used at each power supply pin. (3) with the test condition for v ref = +2.0v (4v p-pa differential input), the 12-bit lsb is 977 v. (4) typical figures are at t a = t j = 25 c, and represent most likely parametric norms. test limits are specified to ti ' s aoql (average outgoing quality level). (5) i is the cur dr rent consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, v dr , and the rate at which the outputs are switching (which is signal dependent). i dr =v dr (c 0 x f 0 + c 1 x f 1 +....c 11 x f 11 ) where v dr is the output driver power supply voltage, c n is total capacitance on the output pin, and f n is the average frequency at which that pin is toggling. (6) excludes i dr . see note 5. copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: adc12010
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com ac electrical characteristics unless otherwise specified, the following specifications apply for agnd = dgnd = dr gnd = 0v, v a = v d = +5v, v dr = +3.0v, pd = 0v, v ref = +2.0v, f clk = 10 mhz, t r = t f = 3 ns, c l = 25 pf/pin. boldface limits apply for t a = t j = t min to t max : all other limits t a = t j = 25 c (1) (2) (3) (4) units symbol parameter conditions typical (5) limits (5) (limits) f clk 1 maximum clock frequency 10 15 mhz (min) f clk 2 minimum clock frequency 100 khz t ch clock high time 30 ns (min) t cl clock low time 30 ns(min) t conv conversion latency 6 clock cycles v dr = 2.5v 11 16.8 ns (max) t od data output delay after rising clk edge v dr = 3.0v 11 16.8 ns (max) t ad aperture delay 1.2 ns t aj aperture jitter 2 ps rms t dis data outputs into tri-state mode 4 ns t en data outputs active after tri-state 4 ns t pd power down mode exit cycle 0.1 f cap on pins 30, 31,32 500 ns (1) the inputs are protected as shown below. input voltage magnitudes above v a or below gnd will not damage this device, provided current is limited per absolute maximum ratings (3) . however, errors in the a/d conversion can occur if the input goes above v a or below gnd by more than 100 mv. as an example, if v a is 4.75v, the full-scale input voltage must be 4.85v to ensure accurate conversions. (2) to ensure accuracy, it is required that |v a ? v| 100 mv and separate bypass capacitors are used at each power supply pin. (3) with the test condition for v ref = +2.0v (4v p-p differential input), the 12-bit lsb is 977 v. (4) timing specifications are tested at ttl logic levels, v dil = 0.4v for a falling edge and v ih = 2.4v for a rising edge. (5) typical figures are at t a = t j = 25 c, and represent most likely parametric norms. test limits are specified to ti ' s aoql (average outgoing quality level). 8 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 specification definitions aperture delay is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. aperture jitter (aperture uncertainty) is the variation in aperture delay from sample to sample. aperture jitter manifests itself as noise in the output. clock duty cycle is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. the specification here refers to the adc clock input signal. common mode voltage (v cm ) is the d.c. potential present at both signal inputs to the adc. conversion latency is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. data for any given sample is available at the output pins the pipeline delay plus the output delay after the sample is taken. new data is available at every clock cycle, but the data lags the conversion by the pipeline delay. differential non-linearity (dnl) is the measure of the maximum deviation from the ideal step size of 1 lsb. effective number of bits (enob, or effective bits) is another method of specifying signal-to-noise and distortion or sinad. enob is defined as (sinad - 1.76) / 6.02 and says that the converter is equivalent to a perfect adc of this (enob) number of bits. full power bandwidth is a measure of the frequency at which the reconstructed output fundamental drops 3 db below its low frequency value for a full scale input. gain error is the deviation from the ideal slope of the transfer function. it is the difference between the positive full scale error and the negative full scale error: gain error = pos. full scale error ? neg. full scale error (1) integral non linearity (inl) is a measure of the deviation of each individual code from a line drawn from negative full scale ( ? lsb below the first code transition) through positive full scale ( ? lsb above the last code transition). the deviation of any given code from this straight line is measured from the center of that code value. intermodulation distortion (imd) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the adc input at the same time. it is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. imd is usually expressed in dbfs. missing codes are those output codes that will never appear at the adc outputs. the adc12010 is ensured not to have any missing codes. negative full scale error is the difference between the actual first code transition and its ideal value of ? lsb above negative full scale. offset error is the difference between the two input voltages (v in + ? v in ? ) required to cause a transition from code 2047 to 2048. output delay is the time delay after the rising edge of the clock before the data update is presented at the output pins. pipeline delay (latency) see conversion latency positive full scale error is the difference between the actual last code transition and its ideal value of 1 ? lsb below positive full scale. power supply rejection ratio (psrr) is a measure of how well the adc rejects a change in the power supply voltage. for the adc12010, psrr1 is the ratio of the change in full-scale error that results from a change in the dc power supply voltage, expressed in db. psrr2 is a measure of how well an a.c. signal riding upon the power supply is rejected at the output. signal to noise ratio (snr) is the ratio, expressed in db, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or dc. copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: adc12010
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com signal to noise plus distortion (s/n+d or sinad) is the ratio, expressed in db, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding dc. spurious free dynamic range (sfdr) is the difference, expressed in db, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. total harmonic distortion (thd) is the ratio, expressed in dbc, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. thd is calculated as (2) where f 1 is the rms power of the fundamental (output) frequency and f 2 through f 10 are the rms power in the first 9 harmonic frequencies. timing diagram figure 1. output timing transfer characteristic figure 2. transfer characteristic 10 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 adc12010 typical performance characteristics v a = v d = 5,0v, v dr = 3.0v, f clk = 10 mhz,f in = 10.1 mhz, v ref = 2.0v unless otherwise stated dnl dnl vs temperature figure 3. figure 4. dnl vs clock duty cycle dnl vs sample rate figure 5. figure 6. inl inl vs temperature figure 7. figure 8. copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: adc12010
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com adc12010 typical performance characteristics (continued) v a = v d = 5,0v, v dr = 3.0v, f clk = 10 mhz,f in = 10.1 mhz, v ref = 2.0v unless otherwise stated inl vs clock duty cycle inl vs sample rate figure 9. figure 10. snr vs temperature snr vs clock duty cycle figure 11. figure 12. snr vs sample rate snr vs f in figure 13. figure 14. 12 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 adc12010 typical performance characteristics (continued) v a = v d = 5,0v, v dr = 3.0v, f clk = 10 mhz,f in = 10.1 mhz, v ref = 2.0v unless otherwise stated snr vs v ref thd vs temperature figure 15. figure 16. thd vs clock duty cycle thd vs sample rate figure 17. figure 18. thd vs f in thd vs v ref figure 19. figure 20. copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: adc12010
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com adc12010 typical performance characteristics (continued) v a = v d = 5,0v, v dr = 3.0v, f clk = 10 mhz,f in = 10.1 mhz, v ref = 2.0v unless otherwise stated sinad vs temperature sinad vs clock duty cycle figure 21. figure 22. sinad vs sample rate sinad vs f in figure 23. figure 24. sinad vs v ref sfdr vs temperature figure 25. figure 26. 14 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 adc12010 typical performance characteristics (continued) v a = v d = 5,0v, v dr = 3.0v, f clk = 10 mhz,f in = 10.1 mhz, v ref = 2.0v unless otherwise stated sfdr vs clock duty cycle sfdr vs sample rate figure 27. figure 28. sfdr vs f in sfdr vs v ref figure 29. figure 30. t od vs v dr spectral response, 1.1 mhz input figure 31. figure 32. copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: adc12010
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com adc12010 typical performance characteristics (continued) v a = v d = 5,0v, v dr = 3.0v, f clk = 10 mhz,f in = 10.1 mhz, v ref = 2.0v unless otherwise stated spectral response, 4.4 mhz input spectral response, 10.1 mhz input figure 33. figure 34. 16 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 functional description operating on a single +5v supply, the adc12010 uses a pipeline architecture with error correction circuitry to help ensure maximum performance. the differential analog input signal is digitized to 12 bits. the reference input is buffered to ease the task of driving that pin. the output word rate is the same as the clock frequency. the analog input voltage is acquired at the rising edge of the clock and the digital data for a given sample is delayed by the pipeline for 6 clock cycles. a logic high on the power down (pd) pin reduces the converter power consumption to 40 mw. copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links: adc12010
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com application information operating conditions we recommend that the following conditions be observed for operation of the adc12010: ? 4.75v v a 5.25v ? v d = v a ? 2.35v v dr v d ? 100 khz f clk 15 mhz ? 1.0v v ref 2.4v ? 1.0v v cm 4.0v analog inputs the adc12010 has two analog signal inputs, v in + and v in ? . these two pins form a differential input pair. there is one reference input pin, v ref . reference pins the adc12010 is designed to operate with a 2.0v reference, but performs well with reference voltages in the range of 1.0v to 2.4v. lower reference voltages will decrease the signal-to-noise ratio (snr). increasing the reference voltage (and the input signal swing) beyond 2.4v will degrade thd for a full-scale input. it is important that all grounds associated with the reference voltage and the input signal make connection to the ground plane at a single point to minimize the effects of noise currents in the ground path. the three reference bypass pins (v rp , v rm and v rn ) are made available for bypass purposes. these pins should each be bypassed to ground with a 0.1 f capacitor. smaller capacitor values will allow faster recovery from the power down mode, but may result in degraded noise performance. do not load these pins. signal inputs the signal inputs are v in + and v in ? . the input signal, v in , is defined as v in = (v in +) ? (v in ? ) (3) figure 35 shows the expected input signal range. note that the common mode input voltage range is 1v to 3v with a nominal value of v a /2. the input signals should remain between ground and 4v. the peaks of the individual input signals (v in + and v in ? ) should each never exceed the voltage described as v in +, v in ? = v ref + v cm (4) to maintain thd and sinad performance. figure 35. expected input signal range the adc12010 performs best with a differential input with each input centered around v cm . the peak-to-peak voltage swing at both v in + and v in ? each should not exceed the value of the reference voltage or the output data will be clipped. the two input signals should be exactly 180 out of phase from each other and of the same amplitude. for single frequency inputs, angular errors result in a reduction of the effective full scale input. for a complex waveform, however, angular errors will result in distortion. 18 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 for angular deviations of up to 10 degrees from these two signals being 180 out of phase, the full scale error in lsb can be described as approximately e fs = 4096 ( 1 - sin (90 + dev)) (5) where dev is the angular difference, in degrees, between the two signals having a 180 relative phase relationship to each other (see figure 36 ). drive the analog inputs with a source impedance less than 100 ? . figure 36. angular errors between the two input signals will reduce the output level for differential operation, each analog input signal should have a peak-to-peak voltage equal to the input reference voltage, v ref , and be centered around a common mode voltage, v cm . table 1. input to output relationship ? differential input v in + v in ? output v cm ? v ref /2 v cm + v ref /2 0000 0000 0000 v cm ? v ref /4 v cm + v ref /4 0100 0000 0000 v cm v cm 1000 0000 0000 v cm + v ref /4 v cm ? v ref /4 1100 0000 0000 v cm + v ref /2 v cm ? v ref /2 1111 1111 1111 table 2. input to output relationship ? single-ended input v in + v in ? output v cm ? v ref v cm 0000 0000 0000 v cm ? v ref /2 v cm 0100 0000 0000 v cm v cm 1000 0000 0000 v cm + v ref /2 v cm 1100 0000 0000 v cm + v ref v cm 1111 1111 1111 single-ended operation single-ended performance is lower than with differential input signals. for this reason, single-ended operation is not recommended. however, if single ended-operation is required, and the resulting performance degradation is acceptable, one of the analog inputs should be connected to the d.c. common mode voltage of the driven input. the peak-to-peak differential input signal should be twice the reference voltage to maximize snr and sinad performance ( figure 35 b). for example, set v ref to 1.0v, bias v in ? to 1.0v and drive v in + with a signal range of 0v to 2.0v. because very large input signal swings can degrade distortion performance, better performance with a single- ended input can be obtained by reducing the reference voltage when maintaining a full-range output. table 1 and table 2 indicate the input to output relationship of the adc12010. driving the analog input the v in + and the v in ? inputs of the adc12010 consist of an analog switch followed by a switched-capacitor amplifier. the capacitance seen at the analog input pins changes with the clock level, appearing as 8 pf when the clock is low, and 7 pf when the clock is high. although this difference is small, a dynamic capacitance is more difficult to drive than is a fixed capacitance, so choose the driving amplifier carefully. the lmh6550, the lmh6702 and the lmh6628 are good amplifiers for driving the adc12010. the internal switching action at the analog inputs causes energy to be output from the input pins. as the driving source tries to compensate for this, it adds noise to the signal. to prevent this, use an rc at each of the inputs, as shown in figure 38 and figure 39 . these components should be placed close to the adc because the input pins of the adc is the most sensitive part of the system and this is the last opportunity to filter the input. the capacitors should be eliminated for undersampling applications. copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 19 product folder links: adc12010
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com the lmh6550 and the lmh6552 are excellent devices for driving the adc12010, especially when single-ended to differential conversion with d.c. coupling is necessary. an example of the use of the lmh6550 to drive the analog input of the adc12010 is shown in figure 38 . for high frequency, narrow band applications, a transformer is generally the recommended way to drive the analog inputs, as shown in figure 39 . input common mode voltage the input common mode voltage, v cm , should be in the range of 0.5v to 4.0v and be of a value such that the peak excursions of the analog signal does not go more negative than ground or more positive than 0.5 volts below the v a supply voltage. the nominal v cm should generally be equal to v ref /2, but v rm can be used as a v cm source as long as v cm need not supply more than 10 a of current. figure 38 shows the use of the v rm output to drive the v cm input of the lmh6550. the common mode output voltage of the lmh6550 is equal to the v cm input input voltage. digital inputs the digital ttl/cmos compatible inputs consist of clk, oe and pd. clk the clk signal controls the timing of the sampling process. drive the clock input with a stable, low jitter clock signal in the range of 100 khz to 15 mhz with rise and fall times of less than 3ns. the trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90 . if the clk is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. this is what limits the lowest sample rate to 100 ksps. the duty cycle of the clock signal can affect the performance of the a/d converter. because achieving a precise duty cycle is difficult, the adc12010 is designed to maintain performance over a range of duty cycles. while it is specified and performance is ensured with a 50% clock duty cycle, performance is typically maintained over a clock duty cycle range of 30% to 70%. the clock line should be terminated at its source in the characteristic impedance of that line. it is highly desirable that the the source driving the adc clk pin only drive that pin. however, if that source is used to drive other things, each driven pin should be a.c. terminated with a series rc to ground, as shown in figure 37 , such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is (6) where t pr is the signal propagation rate down the clock line, "l" is the line length and z o is the characteristic impedance of the clock line. this termination should be as close as possible to the adc clock pin but beyond it as seen from the clock source. typical t pd is about 150 ps/inch (60 ps/cm) on fr-4 board material. the units of "l" and t pd should be the same (inches or centimeters). take care to maintain a constant clock line impedance throughout the length of the line. refer to application note an-905 ( snla035 ) or an-1113 ( snla011 ) for information on setting and determining characteristic impedance. the oe input the oe pin, when high, puts the output pins into a high impedance state. when this pin is low the outputs are in the active state. the adc12010 will continue to convert whether this pin is high or low, but the output can not be read while the oe pin is high. the oe pin should not be used to multiplex devices together to drive a common bus as this will result in excessive capacitance on the data output pins, reducing snr and sinad performance of the converter. see section 3.0. 20 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 pd the pd pin, when high, holds the adc12010 in a power-down mode to conserve power when the converter is not being used. the power consumption in this state is 25 mw with a 10 mhz clock and the output data pins are undefined in this mode. the data in the pipeline is corrupted while in the power down mode. the power down mode exit cycle time is determined by the value of the capacitors on pins 30, 31 and 32. these capacitors loose their charge in the power down mode and must be charged by on-chip circuitry before conversions can be accurate. data outputs the adc12010 has 12 ttl/cmos compatible data output pins. valid offset binary data is present at these outputs while the oe and pd pins are low. while the t od time provides information about output timing, a simple way to capture a valid output is to latch the data on the falling edge of the conversion clock (pin 10). be very careful when driving a high capacitance bus. the more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through v dr and dr gnd. these large charging current spikes can cause on-chip noise that can couple into the analog circuitry, degrading dynamic performance. adequate power supply bypassing and careful attention to the ground plane will reduce this problem. additionally, bus capacitance beyond that specified will cause t od to increase, making it difficult to properly latch the adc output data. the result could be an apparent reduction in dynamic performance. to minimize noise due to output switching, minimize the load currents at the digital outputs. this can be done by connecting buffers (74ac541, for example) between the adc outputs and any other circuitry. only one driven input should be connected to each output pin. additionally, inserting series 100 ? resistors at the digital outputs, close to the adc pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. see figure 37 . while the adc12010 will operate with v dr voltages down to 1.8v, t od increases with reduced v dr . be careful of external timing when using reduced v dr . figure 37. simple application circuit with single-ended to differential buffer copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 21 product folder links: adc12010
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com figure 38. differential drive circuit of figure 37 figure 39. driving the signal inputs with a transformer power supply considerations the power supply pins should be bypassed with a 10 f capacitor and with a 0.1 f ceramic chip capacitor within a centimeter of each power pin. leadless chip capacitors are preferred because they have low series inductance. as is the case with all high-speed converters, the adc12010 is sensitive to power supply noise. accordingly, the noise on the analog supply pin should be kept below 100 mv p-p . no pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. be especially careful of this during turn on and turn off of power. 22 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010 255, 1% 280, 1% 50 : signal input 49.9, 1% 100 pf 511, 1% 511, 1% 150 150 100 pf to adc v in - to adc v in + amplifier: lmh6550 v cm - + - + 511, 1% from adc v rm pin lmv321
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 the v dr pin provides power for the output drivers and may be operated from a supply in the range of 2.35v to v d (nominal 5v). this can simplify interfacing to 3v devices and systems. do not operate the v dr pin at a voltage higher than v d . layout and grounding proper grounding and proper routing of all signals are essential to ensure accurate conversion. maintaining separate analog and digital areas of the board, with the adc12010 between these areas, is required to achieve specified performance. the ground return for the data outputs (dr gnd) carries the ground current for the output drivers. the output current can exhibit high transients that could add noise to the conversion process. to prevent this from happening, the dr gnd pins should not be connected to system ground in close proximity to any of the adc12010's other ground pins. capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. the solution is to keep the analog circuitry separated from the digital circuitry, and to keep the clock line as short as possible. digital circuits create substantial supply and ground current transients. the logic noise thus generated could have significant impact upon system noise performance. the best logic family to use in systems with a/d converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the 74ls, 74hc(t) and 74ac(t)q families. the worst noise generators are logic families that draw the largest supply current transients during clock or signal edges, like the 74f and the 74ac(t) families. in high speed circuits, however, it is often necessary to use these higher speed devices. best performance requires careful attention to pc board layout and to proper signal integrity techniques. the effects of the noise generated from the adc output switching can be minimized through the use of 47 ? to 100 ? resistors in series with each data output line. locate these resistors as close to the adc output pins as possible. figure 40. example of a suitable layout since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. this is because of the skin effect. total surface area is more important than is total ground plane volume. generally, analog and digital lines should cross each other at 90 to avoid crosstalk. to maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. it is important to keep clock lines as short as possible and isolated from all other lines, including other digital lines. even the generally accepted 90 crossing should be avoided with the clock line as even a little coupling can cause problems at high frequencies. this is because other lines can introduce jitter into the clock line, which can lead to degradation of snr. also, the high speed clock can introduce noise into the analog chain. best performance at high frequencies and at high resolution is obtained with a straight signal path. that is, the signal path through all components should form a straight line wherever possible. copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 23 product folder links: adc12010
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com be especially careful with the layout of inductors. mutual inductance can change the characteristics of the circuit in which they are used. inductors should not be placed side by side, even with just a small part of their bodies beside each other. the analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the analog ground plane. figure 40 gives an example of a suitable layout. a single ground plane is recommended with separate analog and digital power planes. the analog and digital power planes should not overlap each other. all analog circuitry (input amplifiers, filters, reference components, etc.) should be placed over the analog power plane. all digital circuitry and i/o lines should be placed over the digital power plane. furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the ground plane at a single point. all ground connections should have a low inductance path to ground.. dynamic performance to achieve the best dynamic performance, the clock source driving the clk input must be free of jitter. isolate the adc clock from any digital circuitry with buffers, as with the clock tree shown in figure 41 . as mentioned in layout and grounding , it is good practice to keep the adc clock line as short as possible and to keep it well away from any other signals. other signals can introduce jitter into the clock signal, which can lead to reduced snr performance, and the clock can introduce noise into other lines. even lines with 90 crossings have capacitive coupling, so try to avoid even these 90 crossings of the clock line. figure 41. isolating the adc clock from other circuitry with a clock tree common application pitfalls driving the inputs (analog or digital) beyond the power supply rails. for proper operation, all inputs should not go more than 100 mv beyond the supply rails (more than 100 mv below the ground pins or 100 mv above the supply pins). exceeding these limits on even a transient basis may cause faulty or erratic operation. it is not uncommon for high speed digital components (e.g., 74f and 74ac devices) to exhibit overshoot or undershoot that goes above the power supply or below ground. a resistor of about 47 ? to 100 ? in series with any offending digital input, close to the signal source, will eliminate the problem. do not allow input voltages to exceed the supply voltage, even on a transient basis. not even during power up or power down. be careful not to overdrive the inputs of the adc12010 with a device that is powered from supplies outside the range of the adc12010 supply. such practice may lead to conversion inaccuracies and even to device damage. attempting to drive a high capacitance digital data bus. the more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through v dr and dr gnd. these large charging current spikes can couple into the analog circuitry, degrading dynamic performance. adequate bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem. additionally, bus capacitance beyond that specified will cause t od to increase, making it difficult to properly latch the adc output data. the result could, again, be an apparent reduction in dynamic performance. 24 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
adc12010 www.ti.com snas185b ? april 2003 ? revised march 2013 the digital data outputs should be buffered (with 74ac541, for example). dynamic performance can also be improved by adding series resistors at each digital output, close to the adc12010, which reduces the energy coupled back into the converter output pins by limiting the output current. a reasonable value for these resistors is 100 ? . using an inadequate amplifier to drive the analog input. as explained in signal inputs , the capacitance seen at the input alternates between 8 pf and 7 pf, depending upon the phase of the clock. this dynamic load is more difficult to drive than is a fixed capacitance. if the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade performance. a small series resistor and shunt capacitor at each amplifier output (as shown in figure 38 and figure 39 ) will improve performance. the lmh6550 , the lmh6702 and the lmh6628 have been successfully used to drive the analog inputs of the adc12010. also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180 o out of phase with each other. board layout, especially equality of the length of the two traces to the input pins, will affect the effective phase between these two signals. remember that an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same device operating in the inverting configuration. operating with the reference pins outside of the specified range. as mentioned in reference pins , v ref should be in the range of 1.0v v ref 2.4v (7) operating outside of these limits could lead to performance degradation. using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals coupled to the clock signal trace. this will cause the sampling interval to vary, causing excessive output noise and a reduction in snr and sinad performance. copyright ? 2003 ? 2013, texas instruments incorporated submit documentation feedback 25 product folder links: adc12010
adc12010 snas185b ? april 2003 ? revised march 2013 www.ti.com revision history changes from revision a (march 2013) to revision b page ? changed layout of national data sheet to ti format .......................................................................................................... 25 26 submit documentation feedback copyright ? 2003 ? 2013, texas instruments incorporated product folder links: adc12010
package option addendum www.ti.com 26-sep-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples adc12010civy/nopb active lqfp ney 32 250 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 85 adc12010 civy (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
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